1. Field of the Invention
This invention relates generally to computer systems and, more specifically, to a system for optimizing bus arbitration latency and method therefor.
2. Description of the Prior Art
Every computer system requires the use of arbiters to determine when certain devices in the computer system may access a particular bus. For example, every Peripheral Component Interconnect (PCI) based system requires an arbiter to determine when each PCI device may access the PCI bus. Current PCI based arbiter designs require a plurality of PCI clock cycles to determine when a particular PCI device should next be granted use of the PCI bus. A plurality of PCI clock cycles is generally required in order to meet PCI specifications. For example, one PCI clock cycle is typically needed to clock in bus request signals from the PCI devices into the arbiter. One or more clock cycles are further required in order for the arbiter to determine which PCI device should be granted the bus next. Another clock cycle is then required to drive all PCI device bus grant signals inactive (i.e., required to meet PCI specifications). Finally, one or more clock cycles are required to assert the next bus grant signal.
As can be seen from the above discussion, several PCI bus cycles are required in order for the arbiter to determine which PCI device should next be granted use of the PCI bus. This arbitration timing needs to be optimized in order to reduce the time it takes for a PCI device to be granted access to the PCI bus. By optimizing the arbitration timing, the time it takes for a PCI device to be granted access to the PCI bus may be substantially reduced. This will speed up the flow of data in the computer system, thereby increasing the overall efficiency of the computer system.
Therefore, a need existed to provide a system to optimize bus arbitration latency. The system needs to reduce the time it takes for a device to be granted access to a bus. This will increase the overall efficiency of the computer system by speeding up the flow of data.